module top(clk,rst,enable,seg_cs,segment,cout);
    input clk,rst,enable;
    output [7:0] segment;
    output [5:0] seg_cs;
    output cout;
    wire clka,clkb;
    wire [3:0] ge,shi;
    fsm u1(.clk(clk),
           .clk_1hz(clka),
           .clk_1khz(clkb));
   counter u2(.clk(clka),
              .rst(rst),
              .en(enable),
              .sec_ge(ge),
              .sec_shi(shi),
              .cout(cout));
  display u3(.clk(clkb),
             .sec_ge(ge),
             .sec_shi(shi),
             .seg_cs(seg_cs),
             .segment(segment));
endmodule
